Random Access Memory (RAM) is a ubiquitous component of modern digital architectures. RAM can be a standalone device or can be integrated in a device that uses the RAM, such as a microprocessor, microcontroller, application specific integrated circuit (ASIC), system-on-chip (SoC), and other like devices. RAM can be volatile or non-volatile. Volatile RAM loses its stored information when power is removed. Non-volatile RAM can maintain memory contents even when power is removed. One type of volatile RAM is Static Random Access Memory (SRAM), which typically uses a bi-stable latching circuit as a memory bit cell.
Modern market forces affect SRAM design and production, and thus there is demand to reduce a physical size of new SRAM designs. To continue doubling the density of SRAM circuits (per Moore's Law) at and below a feature size of 14 nm using CMOS technology, SRAM layout needs to be optimized to allow higher density, higher yield, and lower production costs. Researchers are confronted to come up with cost-effective SRAM layout optimization both at the bit-cell and memory array level.
Conventional six-transistor (6T) SRAM designs, such as FIG. 1's 6T SRAM design 100 having a word line (WL) in a first metal layer and a bit line (BL) in a second metal layer, have staggered and mis-aligned metal islands. When the circuit feature size is 22 nm, the structures depicted in FIG. 1 must be fabricated separately and individually using a fabrication technique known as lithography-etch-lithography-etch (also known as LELE). However, to shrink the feature size smaller than 22 nm, requires triple patterning (i.e., LELELE) with an increased mask count to separately and individually fabricate the staggered and mis-aligned metal islands. The increased number of masks increases fabrication costs, reduces fabrication speed, increases mask count, and decreases fabrication yield.
Accordingly, there are long-felt industry needs for methods and apparatus that improve upon conventional methods and apparatus, including the improved methods and apparatus provided hereby.